Processor and processing method

ABSTRACT

Two path metrics (PM 0 , PM 1 ) are read from path metric storing means  1 , and two path metrics (BM 0 , BM 1 ) are read from branch metric storing means  3 . An ACS operation is executed using PM 0 +MB 0  and PM 1 +BM 1  by comparing means  5 , adding means  6 , comparison result storing means  7 , and selecting means  8 . In parallel with the ACS operation, an ACS operation is executed using PM 0 +MB 1  and PM 1 +BM 0  by comparing means  9 , adding means  10 , comparison result storing means  11 , and selecting means  12.

DESCRIPTION

1. Technical Field

The present invention relates to a processing unit, which isincorporated into a mobile communication apparatus, for performing anASC (Addition, Comparison, and Selection) operation of particularly aViterbi decoding.

2. Background Art

In data communications in a mobile radio communication network, since abit error frequently occurs, an execution of an error correctionprocessing is needed. In the error correction methods, there is a methodin which a convolutional code generated from an input bit is decoded byViterbi decoding on a receiver side. In the error correction processing,a digital signal processor (hereinafter referred to as “DSP”) is used.

The Viterbi decoding repeats the simple processing such as addition,comparison, and selection and performs a trace-back operation forfinally data, thereby realizing a maximum likelihood decoding of theconvolutional code.

The following will briefly explain the Viterbi decoding processing. Theconvolutional code is generated by mode 2 addition of input bits and afixed number of bits precedent thereto. Then, a plurality of coding datais generated to correspond to one bit of the input bits. A number ofinput information bits having influence upon the coding data is calledconstraint length (K). The number of input information bits is equal toa number of stages of shift registers used in mode 2 addition.

The coding data is determined by the input bits and a state of thepreceding (K−1) input bits. When a new information bit is input, thestate of the input bits transits to a new state. The state in whichcoding data transits is determined by whether the new input bit is “0”or “1.” Since the respective (K−1) bits are “1” or “0”, a number ofstates in which coding data transits becomes 2^((K−1)).

In the Viterbi decoding, received coding data sequence is observed, andthe most-likely state is estimated from all obtainable statetransitions. For this reason, every time when coding data (received datasequence) corresponding to one bit of information bits, an inter-signaldistance (metric) of the respective paths to each state at that point iscomputed. Then, operations for leaving a path having a smaller metricamong the paths reaching the same state as a survivor are sequentiallyrepeated.

As shown in a state transition diagram of FIG. 1, in a convolutionalencoder having a constraint length K, two paths each showing a statetransition from each of state S[n] and S[n+2^((K−2))] at one previouspoint extend to a state S[2n] (n=positive integer) at a certain point.For example, in a case of K=3, a transition from each of S[1] (stateS01) and S[3] (state S11) to S[2](state S10) (state in which precedingtwo bits are input in order of “1” and “0”) at the time of n=1 ispossible. Also, at the time of n=2, a transition from each of S[2](state S10) and S[4](state S00) to S[4](state S00) (state shown bylow-order two bits) is possible.

A path metric “a” is a sum of an inter-signal distance (branch metric)“x” between an output symbol of the path inputting to the state S[2n]and the received data sequence and a path metric “A.” The path metric“A” is the total sum of branch metrics of the survivor paths up to thestate S[n] at one previous state. Similarly, a path metric “b” is a sumof an inter-signal distance (branch metric) “y” between an output symbolof the path inputting to the state S[2n] and the received data sequenceand a path metric “B.” The path metric “B” is the total sum of branchmetrics of the survivor paths up to the state S[n+2^((K−2))] at oneprevious point. In the Viterbi decoding, the path metrics “a” and “b ”inputting to the state S[2n] are compared with each other, and thesmaller path is selected as a survivor path.

In the Viterbi decoding, each processing of addition for obtaining thepath metric, comparison between the path metrics and the selection ofpath is executed with respect to 2^((K−2)) states at each point.Moreover, in the selection of path, a history showing which path hasbeen selected is left as a path select signal PS[i], [I=0 to2^((K−2))−1].

At this time, if a subscript (e.g., n) of one previous state of theselected path is smaller than a subscript (n+2^((K−2))) of one previousstate of the non-selected other path, PS[i]=0 is established. If thesubscript (n) it is larger than the subscript (n+2^(K−2))), PS[i]=1 isestablished.

In the case of FIG. 1, since n<(n+2^((K−2))) is established, the stateS[n+2^(K−2))] is selected at the time of a>b and PS[S2n]=1 isestablished, and the state S[n] is selected at the time of a≦b andPS[S2n]=0 is established.

Then, in the Viterbi decoding, data is decoded while being traced backto the path finally survived based on the path select signal.

The following will explain the conventional processing unit for Viterbidecoding, TMS320C54x, which is a general processing unit, (manufacturedby TEXAS INSTRUMENTS, hereinafter referred to as “C54x”) being given asone example. In a GSM cellular radio system, equation (1) set forthbelow is used as a convolutional code.

G1(D)=1+D3+D4

 G2 (D)=1+D+D3+D4  (1)

The above convolutional code is expressed by a trellis diagram of abutterfly structure shown in FIG. 2. The trellis diagram shows a statein which the convolutional code transits from a certain state to anotherstate. Let us assume that constraint length K is 5. States of2^((K−2))=16 or 8 butterfly structures are present for each symbolsection. Then, two branches are input in each state, and a new pathmetric is determined by the ACS operations.

The branch metric can be defined as the following equation (2).

M=SD(2*i)*B(J,0)+SD(2*i+1)*B(j,1)  (2)

where SD(2*i) denotes a first symbol of a symbol metric showing a softdecision input, and SD(2*i+1) denotes a second symbol of the symbolmetric. B(J,0)and B(J,1) conform to codes generated by a convolutionalencoder as shown in FIG. 3.

In C54x, an arithmetic logic section (hereinafter referred to as “ALU”)is set to a dual 16-bit mode, thereby processing the butterfly structureat high speed. The determination of a new path metric (j) can beobtained by calculating two path metrics (2*J and 2*J+1) and the branchmetrics (M and −M) in parallel based on a DSADT instruction andexecuting a comparison based on a CMPS instruction. The determination ofa new path metric (j+8) can be obtained by calculating two path metricsand the branch metrics (M and −M) in parallel based on the DSADTinstruction. The calculation results are stored in high and low orderbits of a double-precision accumulator, respectively.

The CMPS instruction compares the high and low order bits of theaccumulator and stores a larger value in a memory. Also, every time whenthe comparison is executed, which value is selected is written in a16-bit transition register (TRN). The content written to the TRN isstored in the memory every time when each symbol processing is ended.Information to be stored in the memory is used to search a suitable pathin the trace-back processing. FIG. 4 shows a macro program for abutterfly operation of the Viterbi decoding.

The values of the branch metrics are stored in the T register before themacro is called. FIG. 5 shows an example of a memory mapping of the pathmetrics.

8 butterfly operations are executed in one symbol section and 16 newstates are obtained. This series of processing is repeatedly computedover several sections. After the end of the processing, the trace-backis executed so as to search a suitable path from 16 paths. Thereby, adecoding bit sequence can be obtained.

The mechanism of the ACS operations of the C54x, which is the generalDSP, can be thus explained. Then, in C54x, and the updates of two pathmetrics are realized with 4 machine cycles from the example of the macroprogram of FIG. 4.

In the future, there is expected an increase in demand for non-voicecommunications requiring high quality transmission with a lower biterror rate than voice communications. As means for achieving the low biterror rate, there is means for increasing the constraint length K of theViterbi decoding.

However, if the constraint length is increased by a value correspondingto one bit, a number of path metrics (number of states) doubles. Forthis reason, a number of operations in the Viterbi decoding using DSPdouble. Generally, an amount of information in non-voice communicationsis larger than the amount of information in voice communications. If theamount of information increases, the number of operations in the Viterbidecoding including the ACS operation also increases. An increase innumber of operations using DSP makes it difficult to maintain a batteryfor a portable terminal for a long period of time.

For the purpose of downsizing the portable terminal, reducing theweight, and lowering the cost, an area processed by a special LSI hasbeen also designed to be implemented in one chip form using a DSPprocessing in recent years.

However, an increase in the number of operations using DSP exceeds theprocessing capability of the existing DSP, thereby making it impossibleto be implemented in one chip form using DSP.

Moreover, if the function of DSP is highly enhanced to increase thenumber of operations, an increase in the cost of DSP itself is broughtabout. As a result, the reduction in the cost of the portable terminalcannot be realized.

DISCLOSURE OF INVENTION

A first object of the present invention is to provide a processing unitfor efficiently processing an ACS operation of the Viterbi decoding byuse of DSP with a small investment in software.

The above object can be attained by arranging two pairs of comparingsections, an adding section, and a storing section for storing acomparison result in the processing unit and by executing the ACSoperation in parallel.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a trellis diagram showing a path of a state transition of aconvolutional encoder in Viterbi decoding;

FIG. 2 is a schematic diagram showing a butterfly structure of thetrellis diagram;

FIG. 3 is a schematic view showing an example of codes generated by theconvolutional encoder;

FIG. 4 is a program view showing an example of a Viterbi operation forchannel coding;

FIG. 5 is a schematic view showing a pointer control and an example ofpath metric storage;

FIG. 6 is a block diagram showing the structure of the processing unitof the first embodiment of the present invention;

FIG. 7 is a block diagram showing an example of the convolutionalencoder having a code rate 1/2;

FIG. 8 is a schematic view showing the butterfly structure where aconstraint length K=4;

FIG. 9 is a block diagram showing the structure of the processing unitof the second embodiment of the present invention;

FIG. 10 is a timing view explaining a pipe line operation of theprocessing unit of the second embodiment of the present invention;

FIG. 11 is a schematic view showing an example of a memory accessoperation of RAM of the second embodiment of the present invention;

FIG. 12 is a block diagram showing the structure of the processing unitof the third embodiment of the present invention;

FIG. 13 is a schematic view showing an example of a memory accessoperation of a dual port RAM of the third embodiment of the presentinvention;

FIG. 14 is a block diagram showing the structure of the processing unitof the fourth embodiment of the present invention;

FIG. 15 is a timing view explaining a pipe line operation of theprocessing unit of the fourth embodiment of the present invention;

FIG. 16 is a block diagram showing the structure of the processing unitof the fifth embodiment of the present invention;

FIG. 17 is a view showing ACS operation results of the processing unitof the sixth embodiment of the present invention;

FIG. 18 is a block diagram showing the structure of the processing unitof the sixth embodiment of the present invention;

FIG. 19 is a block diagram showing the structure of the processing unitof the seventh embodiment of the present invention;

FIG. 20 is a block diagram showing the structure of the processing unitof the eighth embodiment of the present invention;

FIG. 21 is an input/output view of a 4:2 compressor of the eighthembodiment of the present invention;

FIG. 22 is a block diagram showing the structure of the processing unitof the ninth embodiment of the present invention;

FIG. 23 is a view showing a carry control of a double-precision AU;

FIG. 24 is a block diagram showing the structure of the processing unitof the tenth embodiment of the present invention;

FIG. 25 is a block diagram showing the structure of the processing unitof the eleventh embodiment of the present invention;

FIG. 26 is block diagram showing the structure of a mobile stationapparatus of the twelfth embodiment of the present invention;

FIG. 27 is a block diagram showing the structure of the mobile stationapparatus of the thirteenth embodiment of the present invention;

FIG. 28 a block diagram showing the structure of a base stationapparatus of the fourteenth embodiment of the present invention; and

FIG. 29 a block diagram showing the structure of the base stationapparatus of the fifteenth embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will now be described withreference to the accompanying drawings.

(First Embodiment)

FIG. 6 is a block diagram showing the structure of the processing unitof the first embodiment of the present invention. In FIG. 6, a pathmetric storing section 1 stores path metrics, and a data supply and atransfer of an operation result are executed via a bus 2. A branchmetric storing section 3 stores branch metrics and a data supply isexecuted via a bus 4.

Comparing sections 5 and 9 compare data input from the path metricstoring section 1 and the branch metric storing section 3 via the buses2 and 4, respectively.

Adding sections 6 and 10 add data read from the path metric storingsection 1 and the branch metric storing section 3 via the buses 2 and 4,respectively.

A comparison result storing section 7 stores a comparison result of thecomparing section 5, and a comparison result storing section 11 stores acomparison result of the comparing section 9. Then, the comparisonresult storing sections 7 and 11 transfer the comparison results in thepath metric storing section 1 via the bus 2.

A selecting section 8 inputs an adding result of the adding section 6and determines an output based on the comparison result of the comparingsection 5. A selecting section 12 inputs an adding result of the addingsection 10 and determines an output based on the comparison result ofthe comparing section 9. Then, the selecting sections 8 and 12 transferthe outputs determined based on the comparison results to the pathmetric storing section 1 via a bus 13.

Next, the following will explain ACS operation of the processing unit ofthe first embodiment with reference to the drawings. In the explanationset forth below, it is assumed that data to be decoded is ones that arecoded by a convolutional encoder of FIG. 7 where a constraint length K=4and a code rate 1/2. Also, data type of the path metrics and that of thebranch metrics are single-precision data. Then, when double-precisiondata is set to (X, Y) for the sake of convenience, a high order positionof the double-precision data is set to X and a low order positionthereof is set to Y.

Four branch metrics are set to BM0, BM1, BM2, BM3, respectively. If astate transition is illustrated using these branch metrics, thebutterfly structure is shown as in FIG. 8.

Here, attention should be paid to nodes N0 and N1 of an old state. Thetransition destinations of the nodes N0 and N1 are nodes N′0 and N′4,respectively.

Then, a branch metric, which is obtained at the time of the transitionfrom the node N0 to the node N′0, is BM0, and a branch metric, which isobtained at the time of the transition from the node N1 to the node N′0,is BM1. Also, a branch metric, which is obtained at the time of thetransition from the node N0 to the node N′4, is BM1, and a branchmetric, which is obtained at the time of the transition from the node N1to the node N′4, is BM0.

Thus, the path metric PM1 of the node N0 and the path metric PM1 of thenode N1 are replaced with branch metrics BM0 and BM1, respectively, andthese metrics are added. Thereby, path metric PM′0 of the node N′0 andpath metric PM′4 of the node N′4 are obtained.

Then, this relationship can be applied to the other pairs of nodes (apair of nodes N2 and N3, a pair of nodes N4 and N5, a pair of nodes N6and N7).

The inventor of the present invention paid attention to thisrelationship, and found out that two path metrics could be updatedsimultaneously by processing the ACS operation in parallel and thatprocessing time could be reduced. This led to the present invention.

The ACS operation of the node N′0 to N′3 in the first half is executedby the comparing section 5, the adding section 6, the comparison resultstoring section 7, and the selecting section 8. In parallel with thisoperation, the ACS operation of the node N′4 to N′8 in the second halfis executed by the comparing section 9, the adding section 10, thecomparison result storing section 11, and the selecting section 12. Thefollowing will specifically explain the ACS operation from nodes N0 andN1 to nodes N′0 and N′4.

First, two path metrics (PM1, PM0) are output to the bus 2 from the pathmetric storing section 1. On the other hand, two branch metrics (BM1,BM0) are output to the bus 4 from the branch metric storing section 3.

The comparing section 5 inputs two path metrics (PM1, PM0) from the bus2 and two branch metrics (BM1, BM0) from the bus 4 so as to calculatePM1+BM1−PM0−BM0.

The adding section 6 inputs two path metrics (PM1, PM0) from the bus 2and two branch metrics (BM1, BM0) from the bus 4 so as to calculatePM1+BM1 and PM0+BM0. Then, the calculation results (as PM1+BM1, PM0+BM0)are output to the selecting section 8.

The selecting section 8 inputs the most significant bit (hereinafterreferred to as “MSB”) which is the code bit of the comparison result ofthe comparing section 5, PM1+BM1−PM0−BM0. Then, the selecting section 8selects as to whether the high order PM1+BM1 is output to the bus 13 orthe low order PM0+BM0 is output thereto from the value of the MSB.

In other words, if the equation (3) shown below is established, the MSBis 0 and the selecting section 8 outputs the low order PM0+BM0 to thebus 13 as PM′0. Conversely, if the equation (3) is not established, theMSB is 1 and the selecting section 8 outputs the high order PM1+BM1thereto as PM′0.

 PM1+BM1≧PM0+BM0  (3)

Also, the MSB, which is the comparison result of the comparing section5, is stored in the comparison result storage section 7 at the sametime.

The comparing section 9 inputs two path metrics (PM1, PM0) from the bus2 and two branch metrics (BM1, BM0) from the bus 4 so as to calculatePM1+BM0−PM0−BM1.

The adding section 10 inputs two path metrics (PM1, PM0) from the bus 2and two branch metrics (BM1, BM0) from the bus 4 so as to calculatePM1+BM0 and PM0+BM1. Then, the calculation results (as PM1+BM0, PM0+BM1)are output to the selecting section 12.

The selecting section 12 inputs the MSB of the comparison result of thecomparing section 9, PM1+BM1−PM0−BM1. Then, the selecting section 12selects as to whether the high order PM1+BM0 is output to the bus 13 orthe low order PM0+BM1 is output thereto from the value of the MSB.

In other words, if the equation (4) shown below is established, the MSBis 0 and the selecting section 12 outputs the low order PM0+BM1 to thebus 13 as PM′4. Conversely, if the equation (4) is not established, theMSB is 1 and the selecting section 12 outputs the high order PM1+BM0thereto as PM′4.

PM1+BM0≧PM0+BM1  (4)

Also, the MSB, which is the comparison result of the comparing section9, is stored in the comparison result storage section 11 at the sametime.

The above processing is subjected to the other node pairs in the sameway. As a result, the ACS operation of the Viterbi coding using DSP canbe executed in parallel and the operation processing can be performedwith relatively a small amount of processing at high speed.

The above embodiment explained the case of the constraint length K=4 andthe code rate 1/2. However, even if the constraint length and the coderate are the other values, the above relationship is established.Therefore, the change corresponding thereto is suitably provided, sothat the same advantage can be obtained.

(Second Embodiment)

FIG. 9 is a block diagram showing the structure of the processing unitof the second embodiment of the present invention. In the processingunit of FIG. 9, the same reference numerals are added to the portionscommon to the processing unit of FIG. 6 and the explanation is omitted.

In the processing unit of FIG. 9, the storing section for storing thepath metrics is formed by a RAM 14 having four banks.

The processing unit of FIG. 9 is suitable for the operation processingof a pipeline structure shown in FIG. 10.

For example, for executing the ACS operation at an operation executionstage of n-th+1 cycle in an instruction 1, it is required that addressesof the path metrics to be read at a memory access stage of n-th cycleshould be supplied to the RAM 14 in advance.

It is assumed that the RAM 14 is a double-precision readable RAM thatcan read an even address and an odd address continuously. Then, if thefollowing conditions (a) and (b) are satisfied, two path metrics used inthe operation can be read by only designating the even address.

(a) The path metrics of one state are stored at continuous addresses inorder of the even address and the odd address.

(b) The path metrics of one state are divided into the first and secondhalves, and each is stored in a different bank.

For example, the path metrics (PM0, PM1, PM2, PM3 in FIG. 8) of thefirst half of the old state are stored in the bank 0 of the RAM 14.Then, the path metrics (PM4, PM5, PM6, PM7 in FIG. 8) of the second halfof the old state are stored in the bank 1. In this case, two pathmetrics are generated by executing the ACS operation at one cycle, andthese metrics are stored in banks 2 and 3 via the bus 13, respectively.At this time, double-precision data is transferred from the bus 13, thepath metric of the node N′3 is stored in the bank 2 from the node N′0,and the path metric of the node N′7 is stored in the bank 3 from thenode N′.

FIG. 11 is a schematic view showing an example of a memory accessoperation of the RAM 14 corresponding to FIG. 8.

When the ACS operation of one state is ended, in a next state, the pathmetrics of the old state are read from the banks 2 and 3 and the pathmetrics of a new state are stored in the banks 0 and 1.

Thus, every time when the ACS operation of one state is ended, the pairof banks for reading the path metrics and the pair of banks for storingthe path metrics are switched using RAM 14 having four banks as thestoring section for storing the path metrics. Thereby, the ACS operationof the Viterbi decoding using DSP can be executed in parallel.

In the above explanation, the banks 0 and 1 and the banks 2 and 3 werepaired, respectively. However, even if the other combinations are used,the similar operation can be executed by only changing the address to beused in supplying the metrics at the memory access stage and the addressto be used in storing the metrics. Moreover, in the second embodiment,the RAM 14 was formed by four banks. However, the similar operation canbe executed if the number of banks is more than four.

(Third Embodiment)

FIG. 12 is a block diagram showing the structure of the processing unitof the third embodiment of the present invention. In the processing unitof FIG. 12, the same reference numerals are added to the portions commonto the processing unit of FIG. 6 and the explanation is omitted.

In the processing unit of FIG. 12, the storing section 3 for storing thepath metrics is formed by a dual RAM 15 having three banks.

The processing unit of FIG. 12 is suitable for the operation processingof the pipe line structure shown in FIG. 10.

Since the storing section for storing the path metrics is the dual portRAM 15 in the processing unit of FIG. 12, designation of reading andwriting to the same bank can be executed with one instruction. Forexample, for executing the ACS operation at an operation execution stageof n-th+1 cycle in an instruction 1, an address for reading the pathmetric at a memory access stage of n-th cycle and an address for writingthe path metric are supplied to the dual port RAM 15. Thereby, at then-th+1 cycle, an even address and an odd address can be continuouslyread from the dual port RAM 15 so as to execute the ACS operation.Moreover, one path metric can be written to the same bank.

In the processing unit of the third embodiment, if the followingconditions (a) and (b) are satisfied, two path metrics used in theoperation can be read by only designating the even address.

(a) The path metrics of one state are stored at continuous addresses inorder of the even address and the odd address.

(b) The path metrics of one state are divided into the first and secondhalves, and each is stored in a different bank.

For example, the path metrics (PM0, PM1, PM2, PM3 in FIG. 8) of thefirst half of the old state are stored in the bank 0 of the dual portRAM 15, and the path metrics (PM4, PM5, PM6, PM7 in FIG. 8) of thesecond half of the old state are stored in the bank 1. In this case, twopath metrics are generated by executing the ACS operation at one cycle,and these metrics are stored in banks 0 and 2 via the bus 13,respectively. At this time, the bus 13 transfers double-precision data,the path metric of the node N′3 is stored in the bank 0 from the nodeN′0, and the path metric of the node N′7 is stored in the bank 2 fromthe node N′4.

FIG. 13 is a schematic view showing an example of a memory accessoperation of the RAM 15 corresponding to FIG. 8.

In the processing unit of FIG. 12, when the ACS operation of one stateis ended, only the banks 1 and 2 are switched. Then, the ACS operationof the Viterbi decoding using DSP can be executed in parallel withoutswitching the bank 0.

In the third embodiment, the dual port RAM 15 was formed by three banks.However, the similar operation can be executed if the number of banks ismore than three.

(Fourth Embodiment)

FIG. 14 is ablock diagram showing the structure of the processing unitof the fourth embodiment of the present invention. In the processingunit of FIG. 14, the same reference numerals are added to the portionscommon to the processing unit of FIG. 6 and the explanation is omitted.

The processing unit of FIG. 14 comprises input registers 16 and 17 forinputting data from the bus 2 and for outputting data to the comparingsections 5, 9, and the adding sections 6, 10.

The processing unit of FIG. 14 is suitable for the operation processingof the pipe line structure shown in FIG. 15.

For example, for executing the ACS operation at an operation executionstage of n-th+2 cycle in an instruction 1, an address for reading thepath metric at an memory access stage of n-th cycle is supplied to theRAM 14 in advance. Then, data output from the RAM 14 is latched to theinput registers 16 and 17 via the bus 2 at a data transfer stage ofn-th+1.

The pipe shown in FIG. 15 is structured so that one data transfer stageis inserted between a memory access stage and an operation executionstage of the pipe line shown in FIG. 10. In other words, data outputfrom the RAM 14 is determined at the input registers placed at the frontof the respective operation devices (comparing sections 5, 9, and addingsections 6, 10) at a starting point of the operation execution stage. Asa result, time required for data transfer from the RAM 14 can beomitted.

Therefore, according to this embodiment, the ACS operation of theViterbi decoding using DSP can be executed in parallel at relativelyhigh speed. Note that the similar operation can be executed if the dualport RAM is used as the storing section for storing the path metrics.

(Fifth Embodiment)

FIG. 16 is a block diagram showing the structure of the processing unitof the fifth embodiment of the present invention. In the processing unitof FIG. 16, the same reference numerals are added to the portions commonto the processing unit of FIG. 14 and the explanation is omitted.

In the processing unit of FIG. 16, a swap circuit 18 is added ascompared with the processing unit of FIG. 14. The swap circuit 18directly outputs data input from the branch metric storing section 3 orswaps the high order position and the low order position so as to beoutput.

The processing unit of FIG. 16 is suitable for the operation processingof the pipe line structure shown in FIG. 15.

For example, let us assumed that data is input as double-precision datain a form of {BM1, BM0} from the branch metric storage 3. In this case,the swap circuit 18 has a function of switching whether values of twobranch metrics are directly output as {BM1, BM0} or the high orderposition and the low order position are swapped so as to be output as{BM0, BM1} by an instruction.

The following will explain an operation of the swap circuit 18 using theconvolutional encoder of FIG. 7 and the path metric transition state ofthe butterfly structure of FIG. 8 where the constraint length K=4 andthe code rate is 1/2.

As shown in FIG. 17, the ACS operation, which is executed at the time ofthe transition from the nodes N0 and N1 of the old state to the nodesN′0 and N′4, and the ACS operation, which are executed at the time ofthe transition from the nodes N6 and N7 of the old state to the nodesN′3 and N′7, are compared with each other. As a result, in both ACSoperations, common branch metrics BM0 and BM1 are used and therelationship in which BM0 and BM1 are swapped is established.

The ACS operation, which is executed at the time of the transition fromthe nodes N0 and N1 to the node N′0, and the ACS operation, which isexecuted at the time of the transition from the nodes N6 and N7 to thenode N′3 are performed by the comparing section 5 and the adding section6. On the other hand, the ACS operation, which is executed at the timeof the transition from the nodes N3 and N1 to the node N′4, and the ACSoperation, which is executed at the time of the transition from thenodes N6 and N7 to the node N′7, are performed by the comparing section9 and the adding section 10.

For this reason, if the branch metrics are stored in the branch metricstoring section 3 in both forms of {BM0, BM1} and {BM1, BM0}, the branchmetric storing section 3 results in a redundant hardware source.

The swap circuit 18 is used to solve such redundancy. For example, thebranch metrics are stored in the branch metric storing section 3 in onlythe form of {BM0, BM1}. Then, the metrics in the form of {BM0, MB1} areinput to the swap circuit 18. The swap circuit 18 swaps the metrics inthe form of {BM0, BM1} or the metrics in the form of {BM1, BM0} so as tobe output by an instruction. Thereby, redundancy of the branch metricstoring section 3 can be omitted.

The above embodiment was explained using the nodes N0, N1, N6, N7 of theold state where the constraint length K=4 and the code rate was 1/2.However, the aforementioned relationship can be established using eventhe nodes N2, N3, N4, N5. Also, the aforementioned relationship can beestablished using the other combinations of the constraint length K andthe code rate. Therefore, the similar operation can be executed.Moreover, the similar operation can be executed even if the dual portRAM is used as the storing section for storing the path metrics.

(Sixth Embodiment)

FIG. 18 is a block diagram showing the structure of the processing unitof the sixth embodiment of the present invention. In the processing unitof FIG. 18, the same reference numerals are added to the portions commonto the processing unit of FIG. 16 and the explanation is omitted.

As compared with the processing unit of FIG. 16, in the processing unitof FIG. 18, the comparing section 5 comprises adders 19, 20, and acomparator 21, and the adding section 6 comprises adders 22 and 23.Also, the comparing section 9 comprises adders 24, 25, and a comparator26, and the adding section 10 comprises adders 27 and 28.

In FIG. 18, the adders 19 and 20 input data from the bus 4 and the inputregister 16 and add these input data. The comparator 21 inputs additionresults from the adders 19 and 20 and compares the addition results, andoutputs a comparison result to the comparison result storing section 7and the selecting section 8. The adders 22 and 23 input data from thebus 4 and the input register 16 and add these input data, and outputaddition results to the selecting section 8.

The adders 24 and 25 input data from the bus 4 and the input register 17and add these input data. The comparator 26 inputs addition results fromthe adders 24 and 25 and compares the addition results, and outputs acomparison result to the comparison result storing section 11 and theselecting section 12. The adders 27 and 28 input data from the bus 4 andthe input register 17 and add these input data, and output additionresults to the selecting section 12.

The processing unit of FIG. 18 is suitable for the operation processingof the pipe line structure shown in FIG. 15.

Next, the ACS operation of the sixth embodiment will be explained. Thisexplanation will be given using the convolutional encoder of FIG. 7 andthe butterfly structure of FIG. 8 where the constraint length K=4 andthe code rate is 1/2, and the ACS operation result of FIG. 17.

As shown in FIG. 18, two metrics are output as {A, B} from the inputregisters 16 and 17, and two branch metrics are output as {C, D} fromthe swap circuit 18. At this time, the adder 19 inputs the path metric{A} and the branch metric {C}, and outputs an addition result {A+C}. Theadder 20 inputs the path metric {B} and the branch metric {D}, andoutputs an addition result {B+D}. The comparator 21 inputs the additionresult {A+C} of the adder 19 and the addition result {B+D} of the adder20, compares {A+C−(B+D)}, and outputs the MSB of the comparison result.The adder 22 inputs the path metric {A} and the branch metric {C}, andoutputs the addition result {A+C}. The adder 23 inputs the path metric{B} and the branch metric {D}, and outputs the addition result {B+D}.

On the other hand, the adder 24 inputs the path metric {A} and thebranch metric {D}, and outputs an addition result {A+D}. The adder 25inputs the path metric {B} and the branch metric {C}, and outputs anaddition result {B+C}. The comparator 26 inputs the addition result{A+D} of the adder 24 and the addition result {B+C} of the adder 25,compares {A+D−(B+C)}, and output the MSB of the comparison result. Theadder 27 inputs the path metric {A} and the branch metric {D}, andoutputs the addition result {A+D}. The adder 28 inputs the path metric{B} and the branch metric {C}, and outputs the addition result {B+C}.

By the above structure and the operation, if two path metrics of theinput registers 16 and 17 are set to {A,B}={PM1,PM0} and the outputs ofthe swap circuit 18 are set to {C,D} ={BM1,BM0}, the ACS operation,which is executed at the time of the transition from the nodes N0 and N1of the old state to the nodes N′0 and N′4, can be realized.

Also, if two path metrics of the input registers 16 and 17 are set to{A,B}={PM1,PM0} and the outputs of the swap circuit 18 are set to{C,D}={BM0,BM1}, the ACS operation, which is executed at the time of thetransition from the nodes N0 and N1 of the old state to the nodes N′0and N′4, can be realized.

Therefore, according to the sixth embodiment, the update of two pathmetrics can be realized at one machine cycle by the pipe line operationusing DSP. The above embodiment was explained using the nodes N0, N1,N6, N7 of the old state where the constraint length K=4 and the coderate was 1/2. However, the aforementioned relationship can beestablished using even the nodes N2, N3, N4, N5. Also, theaforementioned relationship can be established using the othercombinations of the constraint length K and the code rate. Therefore,the similar operation can be executed. Moreover, the similar operationcan be executed even if the dual port RAM is used as the storing sectionfor storing the path metrics.

(Seventh Embodiment)

FIG. 19 is a block diagram showing the structure of the processing unitof the seventh embodiment of the present invention. In the processingunit of FIG. 19, the same reference numerals are added to the portionscommon to the processing unit of FIG. 18 and the explanation is omitted.

As compared with the processing unit of FIG. 18, in the processing unitof FIG. 19, an arithmetic logic section (hereinafter referred as “ALU”)29 is used in place of the comparator 21. Then, the processing unit ofFIG. 19 comprises input registers 30, 31, buses 32, 33, 37, 38, andselectors 34 and

In FIG. 19, the register 30 inputs data from the RAM 14 via the bus 37.The register 31 inputs data from the RAM 14 via the bus 38. The buses 32and 33 input data from a register file 36. The selector 34 selects anoutput of input data from the bus 32, the adder 19, and the inputregister 30. The selector 35 selects an output of input data from thebus 33, the adder 20, and the input register 31. The ALU 29 inputs datafrom the selectors 34 and 35 and executes an arithmetic logic operation,and outputs a result of the arithmetic logic operation to the bus 13.Also, the ALU 29 outputs the MSB of the result of the arithmetic logicoperation to the comparison result storing section 7 and the selectingsection 8.

The processing unit of FIG. 19 is suitable for the operation processingof the pipe line structure shown in FIG. 15.

In the case where the ALU 29 performs the ACS operation, the selector 34selects an output of the adder 19 and inputs the selected output to theALU 29. The selector 35 selects an output of the adder 20 and inputs theselected output to the ALU 29. Then, the ALU 29 subtracts input twodata, and the MSB of the subtraction result to the comparison resultstoring section 7 and the selecting section 8.

In the case where the ALU 29 performs the arithmetic logic operationbetween the register-register, the selectors 34 and 35 select the buses32 and 33, respectively. Then, data, which is output to the buses 32 and33 from the register file 36, is input to the ALU 29.

Also, in the case where the ALU 29 performs the arithmetic logicoperation between the register-memory, the selectors 34 and 35 selectthe bus 32 and the input register 31, respectively. Then, data, which isoutput to the bus 32 from the register file 36, and data, which isoutput to the input register 31 from the RAM 14 via the bus 38, areinput to the ALU 29.

Conversely, in the case where the ALU 29 performs the arithmetic logicoperation between the memory-register, the selectors 34 and 35 selectthe input register 30 and the bus 33, respectively. Then, data, which isoutput to the register 30 from the RAM 14 via the bus 37, and data,which is output to the bus 33 from the register file 36, are input tothe ALU 29.

Also, in the case where the ALU 29 performs the arithmetic logicoperation between the memory—memory, the selectors 34 and 35 select theinput registers 30 and 31, respectively. Then, data, which is input tothe input registers 30 and 31 from the RAM 14 via the buses 37 and 38,is input to the ALU 29.

Thus, according to the seventh embodiment, for implementing theprocessing unit in an LSI form, one of the comparators for executing theACS operations is used as ALU. Thereby, a chip area can be decreased,and the manufacturing cost can be reduced. Note that the similaroperation can be executed even if the dual port RAM is used as thestoring section for storing the path metrics.

(Eighth Embodiment)

FIG. 20 is a block diagram showing the structure of the processing unitof the eighth embodiment of the present invention. In the processingunit of FIG. 20, the same reference numerals are added to the portionscommon to the processing unit of FIG. 19 and the explanation is omitted.

As compared with the processing unit of FIG. 19, in the processing unitof FIG. 20, two adders 19 and 20 are formed by a 4:2 compressor 39, andtwo adders 24 and 25 are formed by a 4:2 compressor 40. In the4:2compressors 39 and 40, single blocks, shown in FIG. 21, correspondingto a number of single precision bits, are connected in series. The 4:2compressors 39 and 40 execute an addition processing at higher speedthan the general full adders.

In FIG. 20, the 4:2 compressor 39 inputs data from the bus 4 and theinput register 16, and outputs an operation result to the selectors 34and 35. The 4:2 compressor 40 inputs data from the bus 4 and the 3 inputregister 17, and outputs an operation result to the comparator 26.

The processing unit of FIG. 20 is suitable for the operation processingof the pipe line structure shown in FIG. 15.

Next, the ACS operation of the eighth embodiment will be explained. Thisexplanation will be given using the convolutional encoder of FIG. 7 andthe butterfly structure of FIG. 8 where the constraint length K=4 andthe code rate is 1/2, and the ACS operation result of FIG. 17.

First of all, two metrics are output as {A, B} from the input registers16 and 17, and two branch metrics are output as {C, D} from the swapcircuit 18.

Then, the 4:2 compressor 39 inputs the path metric {A} and the branchmetric {C}, a reverse {^(—)B} for path metric {B}, and a reverse {^(—)D}for branch metric D, and outputs {A+C} and {B+D}. Two outputs {A+C} and{B+D} of the 4:2 compressor 39 are input to the ALU 29 via the selectors34 and 35 so as to be added. In this case, to realize two complements{B} and {D}, “1” is input to the 4:2 compressor 39 and the leastsignificant carry input of the ALU 29. As a result, {A+C−(B+D)} isobtained and the MSB is output from the ALU 29.

Also, the adder 22 inputs the path metric {A} and the branch metric {C},and outputs the addition result {A+C}. Similarly, the adder 23 inputsthe path metric {B} and the branch metric {D}, and outputs the additionresult {B+D}.

On the other hand, the 4:2 compressor 40 inputs the path metric {A} andthe branch metric {D}, a reverse {^(—)B} for path metric {B}, and areverse {_C} for branch metric C, and outputs {A+C} and {B+D}. Twooutputs {A+C} and {B+D} of the 4:2 compressor 40 are input to thecomparator 26 so as to be added. In this case, to realize twocomplements {B} and {C}, “1” is input to the 4:2 compressor 40 and theleast significant carry input of the comparator 26. As a result,{A+D−(B+C)} is obtained and the MSB is output from the comparator 26.

Also, the adder 27 inputs the path metric {A} and the branch metric {D},and outputs the addition result {A+D}. Similarly, the adder 28 inputsthe path metric {B} and the branch metric {C}, and outputs the additionresult {B+C}.

By the above structure and the operation, if two path metrics {A,B} ofthe input registers 16 and 17 are set to {PM1,PM0} and the outputs {C,D}of the swap circuit 18 are set to {BM1,BM0}, the ACS operation, which isexecuted at the time of the transition from the nodes N0 and N1 of theold state of FIG. 17 to the nodes N′0 and N′4, can be realized.

Also, if two path metrics {A,B} of the input registers 16 and 17 are setto {PM1,PM0} and the outputs {C,D} of the swap circuit 18 are set to{BM0,BM1}, the ACS operation, which is executed at the time of thetransition from the nodes N0 and N1 of the old state of FIG. 17 to thenodes N′0 and N′4, can be realized. Therefore, the update of two pathmetrics can be realized at one machine cycle by the pipe line operationusing DSP.

Thus, according to the eighth embodiment, the use of the 4:2 compressorsas the comparing section for executing the ACS operation can realize thehigher speed computation than the case using two adders. The aboveembodiment was explained using the nodes N0, N1, N6, N7 of the old statewhere the constraint length K=4 and the code rate was 1/2. However, theaforementioned relationship can be established using even the nodes N2,N3, N4, N5. Also, the aforementioned relationship can be establishedusing the other combinations of the constraint length K and the coderate. Therefore, the similar operation can be executed. Moreover, thesimilar operation can be executed even if the dual port RAM is used asthe storing section for storing the path metrics.

(Ninth Embodiment)

FIG. 22 is a block diagram showing the structure of the processing unitof the seventh embodiment of the present invention. In the processingunit of FIG. 22, the same reference numerals are added to the portionscommon to the processing unit of FIG. 20 and the explanation is omitted.

As compared with the processing unit of FIG. 20, in the processing unitof FIG. 22, double-precision adders 41 and 42 are used as addingsections, and at least one of the adders uses a double-precision AU 41.

In FIG. 22, the double-precision AU 41 inputs data in a double-precisionform from the input register 16 and the bus 4 and executes adouble-precision arithmetic operation. The double-precision adder 42inputs data in a double-precision form from the input register 17 andthe bus 4 and executes a double-precision adding operation. Thedouble-precision AU 41 outputs an operation result to the selectingsection 8 and the bus 13, and the output of the double-precision adder42 is output to the selecting section 12.

The processing unit of FIG. 22 is suitable for the operation processingof the pipe line structure shown in FIG. 15.

For executing the ACS operation in the ninth embodiment, thedouble-precision AU 41 inputs two path metrics as {A, B} in adouble-precision form from the input register 16. Then, thedouble-precision AU 41 inputs two branch metrics as {C, D} in adouble-precision form from the swap circuit 18 via the bus 4, andexecutes a double-precision addition. At this time, the double-precisionAU 41, as shown in FIG. 23, forcibly zeros the carry from the bitposition of the single-precision MSB to a next stage, and executes twoadditions of the path metrics and the branch metrics, {A+C, B+D},simultaneously.

On the other hand, the double-precision adder 42 inputs two path metricsas {A, B} in a double-precision form from the input register 17. Then,the double-precision adder 42 inputs two branch metrics as {D, C} in adouble-precision form from the swap circuit 18 via the bus 4. Then, thedouble-precision adder 42 forcibly zeros the carry from the bit positionof the single-precision MSB to a next stage, and executes two additionsof the path metrics and the branch metrics, {A+C, B+D}, simultaneously.

Thus, according to the ninth embodiment, the double-precision AU 41 isused as the adding section for executing the ACS operation. At the timeof the ACS operation, the double-precision AU 41 forcibly zeros thecarry from the bit position of the single-precision MSB to the nextstage. At the time of the double-precision arithmetic operation otherthan the ACS operation, the control for propagating the carry is added.Thereby, for example, the double-precision AU 41 can be used as adouble-precision accumulation adder at the time of product and additionoperations. Therefore, in the case of implementing the processing unitin an LSI form, the chip area can be further decreased, and themanufacturing cost can be reduced. Note that the similar operation canbe executed even if the dual port RAM is used as the storing section forstoring the path metrics.

(Tenth Embodiment)

FIG. 24 is a block diagram showing the structure of the processing unitof the tenth embodiment of the present invention. In the processing unitof FIG. 24, the same reference numerals are added to the portions commonto the processing unit of FIG. 22 and the explanation is omitted.

As compared with the processing unit of FIG. 22, in the processing unitof FIG. 20, shift registers 43 and 44 are used as a comparison resultstoring section.

In FIG. 24, the shift register 43 inputs the MSB of the operation resultof the ALU 29 so as to be output to the bus 2. The shift register 44inputs the MSB of the operation result of the comparator 26 so as to beoutput to the bus 2.

The processing unit of FIG. 24 is suitable for the operation processingof the pipe line structure shown in FIG. 15.

For executing the ACS operation in the tenth embodiment, the BSM of thecomparison result of the ALU 29 is shifted in the shift register 43 atany time. The BSM of the comparison result of the comparator 26 isshifted in the shift register 44 at any time. Thereby, a path selectsignal can be stored in the RAM 14. In this case, the path select signalshows which path of two paths has been selected, and is used inexecuting the trace-back after the end of the ACS operation.

For example, in a case where the bit width of the shift register 43 andthat of the shift register 44 are single-precision data widths, the pathselect signal can be stored when the ACS operation corresponding to anumber of single-precision bits are executed.

Thus, according to the tenth embodiment, the shift registers are used asstoring means for executing the ACS operations and for storing thecomparison result. Thereby, for example, the shift registers can be usedas an operation instruction for using a shift register of a divisionsystem. Therefore, in the case of implementing the processing unit in anLSI form, the chip area can be further decreased, and the manufacturingcost can be reduced. Note that the similar operation can be executedeven if the dual port RAM is used as the storing section for storing thepath metrics.

(Eleventh Embodiment)

FIG. 25 is ablock diagram showing the structure of the processing unitof the eleventh embodiment of the present invention. In the processingunit of FIG. 25, the same reference numerals are added to the portionscommon to the processing unit of FIG. 24 and the explanation is omitted.

As compared with the processing unit of FIG. 24, in the processing unitof FIG. 25, the input register 17 swaps the path metric data so as to beinput from the bus 2. Then, 4:2 compressor 40 directly inputs the branchmetric data without swapping the branch metric data, and a negate valueof the comparison result of the comparator 26 is shifted in the shiftregister 44.

The processing unit of FIG. 25 is suitable for the operation processingof the pipe line structure shown in FIG. 15.

For executing the ACS operation in this embodiment, two path metrics{A,B} are directly input to the input register 16 as {A,B}, and input tothe input register 17 as {B,A} in a swapped state. After that, twobranch metrics are input from the swap circuit 18 to the 4:2 compressor40 as {C} and {^(—)D}, and two path metrics are input from the inputregister 17 to the 4:2 compressor 40 as {B} and {^(—)A}, and {A+B} and{B+C} are output.

Then, the comparator 26 inputs two outputs {A+B} and {B+C} so as tocalculate {A+D−B−C}

On the other hand, the double-precision adder 42 inputs two branchmetrics as {C, D} from the swap circuit 18, and inputs two path metricsas {B, A} from the input register. Then, {B+C} and {A+D} aresimultaneously computed in parallel, and output to the selecting section12 in the form of {B+C, A+D}.

Then, the MSB of the comparison result is output to the selectingsection 12 from the comparator 26, and the MSB of the negate value ofthe comparison result is output to the shift register 44.

Thus, according to the eleventh embodiment, one of the input registersfor storing two path metrics swaps data to be input. As a result, sincethe need of the swapping operation at the input of the 4:2 compressor 40and that of the double-precision adder 42 can be eliminated at theoperation execution (EX) stage, the ACS operation can be executed athigher speed. Note that the similar operation can be executed even ifthe dual port RMA is used as the means for storing the path metrics.

(Twelfth Embodiment)

FIG. 26 is a block diagram showing the structure of a mobile stationapparatus in the twelfth embodiment. A mobile station apparatus 45 shownin FIG. 26 comprises an antenna section 46 for both reception andtransmission, a radio section 47 having a receiving section 48 and atransmitting section 49, a base band signal processing section 50 forexecuting a signal modulation and demodulation, and a signal coding anddecoding, a speaker 58 for outputting a sound, a microphone 59 forinputting a sound, a data input/output section 60 forinputting/outputting data to be received and transmitted from/to anouter device, a display section 61 for displaying an operation state, anoperation section 62 such as a 10-button keypad, and a control section63 for controlling the respective parts.

The base band signal processing section 50 comprises a demodulationsection 51 for demodulating a received signal, a modulation section 52for modulating a transmitted signal, and a DSP 53 of one chip.

The DSP 53 comprises a Viterbi decoding section 55, which is formed byany one of the processing units of the first to eleventh embodiments, aconvolutional coding section 56 for convolutional coding the transmittedsignal, a voice codec section 57 for executing a voice signal coding anddecoding, and a timing control section 54 for controlling timing forsending the received signal to the Viterbi decoding section 55 from thedemodulation section 51 and timing for sending the transmitted signal tothe modulation section 52 from the convolutional coding section 56.These devices are formed by software, respectively.

The control section 63 displays a signal input from the operationsection 62 to the display section 61, receives the signal input from theoperation section 62. Then, the control section 63 outputs a controlsignal for performing a calling operation to the antenna section 46, theradio section 47, and the base band signal processing section 50 inaccordance with a communication sequence.

If the voice is transmitted from the mobile station apparatus 45, thevoice signal input from the microphone 59 is AD converted by an ADconverter (not shown). Then, the converted signal is coded by the voicecodec section 57 so as to be input to the convolutional coding section56. If data is transmitted, data input from the outer section is inputto the convolutional coding section 56 through the data input/outputsection 60.

Data input to the convolutional coding section 56 is convolutionalcoded, and the timing control section 54 sorts data and adjusts thetransmission output timing so as to output data to the modulationsection 52. Data input to the modulation section 52 is digitallymodulated, AD converted, and output to the transmitting section 49 ofthe radio section 47. Data input to the transmitting section 49 isconverted to radio signals, and output to the antenna section 46 asradio waves.

On the other hand, for outputting data received by the mobile stationapparatus 45, the radio waves received by the antenna portion 46 arereceived by the receiving section 48 of the radio potion 47, ADconverted, and output to the demodulation section 51 of the base bandsignal processing section 50. Data demodulated by the demodulationsection 51 is sorted by the timing control section 54, thereafter beingdecoded by the Viterbi decoding section 55.

In the case of voice communications, decoded data is voice decoded bythe voice codec section 57, and is DA converted, thereafter being outputto the speaker 58 as a voice. In the case of data communications, datadecoded by the Viterbi decoding section 55 is output to the outersection through the data input/output section 60.

In the mobile station apparatus 45 of the twelfth embodiment, therespective parts of the Viterbi decoding section 55, the convolutionalcoding section 56, the voice codec section 57, and the timing controlsection 54 are formed by software of one chip DSP 53. Thus, the mobilestation apparatus 45 can be assembled by a small number of parts. Also,since the Viterbi decoding section 55 is formed by any one of theprocessing units of the first to eleventh embodiments, the update of twopath metrics can be realized with one machine cycle in the pipe lineprocessing using DSP 53. Thereby, the high speed ACS operation of theViterbi decoding using DSP 53 can be realized with relative a smallamount of processing.

In this embodiment, the demodulation section 51 and the modulationsection 52 are shown to be differentiated from DSP 53. However, thesedevices can be formed by software of DSP 53. Also, the DSP of the sixthembodiment can be used as DSP 53, and the convolutional coding section56, the voice codec section 57, and the timing control section 54 can beformed by the other parts, respectively.

(Thirteenth Embodiment)

FIG. 27 is a block diagram showing the structure of a mobile stationapparatus in the thirteenth embodiment. In a mobile station apparatus45A of FIG. 27, the same reference numerals are added to the portionscommon to the portions of the mobile station apparatus 45 of FIG. 26,and the explanation is omitted.

As compared with the mobile station apparatus 45 of FIG. 26, in themobile station apparatus 45A of FIG. 27, a spreading section 65 isprovided in a modulation section 52A, and a despreading section 64 isprovided in a demodulation section 51A, so that a base band signalprocessing section 50A of a CDMA communication system is formed. In thecase of the CDMA communication system, in some cases, a RAKE receivingsection, in which a plurality of fingers selected from a delay profileare adjusted to each other, is included in the timing control section54.

Thus, in the mobile station apparatus 45A in the thirteenth embodiment,the despreading section 64 is provided in the demodulation section 51Aand the spreading section 65 is provided in the modulation section 52A.Thereby, the mobile station apparatus 45A of the thirteenth embodimentcan be applied to the CDMA communication system.

(Fourteenth Embodiment)

FIG. 28 is a block diagram showing the structure of a base stationapparatus in the fourteenth embodiment.

In FIG. 28, a base station apparatus 68 of the fourteenth embodimentcomprises the antenna section 46 having an antenna 66 for receiving andan antenna 67 for transmitting, the radio section 47 having thereceiving section 48 and the transmitting section 49, a base band signalprocessing section 69 for executing a signal modulation and demodulationand a signal coding and decoding, the data input/output section 60 forinputting/outputting data to be received and transmitted from/to a cablenetwork, and the control section 63 for controlling the respectiveparts.

The base band signal processing section 69 comprises the demodulationsection 51 for demodulating the received signal, the modulation section52 for modulating the transmitted signal, and one chip DSP 53A. The DSP53A comprises the Viterbi decoding section 55, which is formed by anyone of the processing units of the first to eleventh embodiments, theconvolutional coding section 56 for convolutional coding the transmittedsignal, and the timing control section 54 for controlling timing forsending the received signal to the Viterbi decoding section 55 from thedemodulation section 51 and timing for sending the transmitted signal tothe modulation section 52 from the convolutional coding section 56.These devices are formed by software, respectively.

When data is received to the base station apparatus 68 from the cablenetwork, data is input to the convolutional coding section 56 throughthe data input/output section 60. Then, data input to the convolutionalcoding section 56 is convolutional coded, and the timing control section54 sorts input data and adjusts the transmission output timing so as tooutput data to the modulation section 52. Data input to the modulationsection 52 is digitally modulated, AD converted, and is converted toradio signals by the transmitting section 49. Then, the radio signalsare transmitted from the antenna section 46 as radio waves.

On the other hand, if data is received to the base station apparatus 68from the radio network, the radio waves received by the antenna portion46 are AD converted by the receiving section 48 and demodulated by thedemodulation section 51 of the base band signal processing section 69.Demodulated data is sorted by the timing control section 54, and decodedby the Viterbi decoding section 55, thereafter being output to the cablenetwork via the data input/output section 60.

In the base station apparatus 68 of the fourteenth embodiment, therespective parts of the Viterbi decoding section 55, the convolutionalcoding section 56, and the timing control section 54 are formed bysoftware of one chip DSP 53A. Thus, the base station apparatus 68 can beassembled by a small number of parts. Also, since the Viterbi decodingsection 55 is formed by any one of the processing units of the first toeleventh embodiments, the update of two path metrics can be realizedwith one machine cycle in the pipe line processing using DSP 53A.Thereby, the high speed ACS operation of the Viterbi decoding using DSP53A can be realized with relatively a small amount of processing.

In this embodiment, the demodulation section 51 and the modulationsection 52 are shown to be differentiated from DSP 53A. However, thesedevices can be formed by software of DSP 53A. Also, the DSP of the sixthembodiment can be used as DSP 53A, and the convolutional coding section56, the voice codec section 57, and the timing control section 54 can beformed by the other parts, respectively.

(Fifteenth Embodiment)

FIG. 29 is a block diagram showing the structure of a base stationapparatus in the fifteenth embodiment. In a base station apparatus 68Aof FIG. 29, the same reference numerals are added to the portions commonto the portions of the base station apparatus 68 of FIG. 28, and theexplanation is omitted.

As compared with the mobile station apparatus 45 of FIG. 26, in themobile station apparatus 45A of FIG. 27, the spreading section 65 isprovided in the modulation section 52A, and the despreading section 64is provided in the demodulation section 51A, so that the base bandsignal processing section 50A of the CDMA communication system isformed. In the case of the CDMA communication system, in some cases, theRAKE receiving section, in which the plurality of fingers selected fromthe delay profile are adjusted to each other, is included in the timingcontrol section 54.

Thus, in the base station apparatus 68A of the fifteenth embodiment, thedespreading section 64 is provided in the demodulation section 51A andthe spreading section 65 is provided in the modulation section 52A.Thereby, the base station apparatus 68A of the fifteenth embodiment canbe applied to the CDMA communication system.

As mentioned above, the update of two path metrics can be realized withone machine cycle in the pipe line processing using DSP. Thereby, thehigh speed ACS operation of the Viterbi decoding using DSP can berealized with relative a small amount of processing. This makes itpossible to downsize the portable terminal, reducing the weight,lowering the cost, and increasing the life of a battery.

What is claimed is:
 1. A processing unit comprising: a path metricstorage apparatus that stores path metrics; a branch metric storageapparatus that stores branch metrics; and two ACS input units that inputtwo path metrics representing the states of 2N and 2N+1, where N=0,1, .. . , 2^(k−2)−1 and where K represents a constraint length and twobranch metrics to execute ACS operations, and for writing operationresults to said path metric storage apparatus.
 2. A processing unitcomprising: a path metric storage apparatus that stores path metrics;branch metric storage apparatus that stores branch metrics; and two ACSinput units that input two path metrics and two branch metrics toexecute ACS operations, and for writing operation results to said pathmetric storage apparatus, wherein one ACS input unit executes the ACSoperation using a value obtained by adding a first branch metric to afirst path metric and a value obtained by adding a second branch metricto a second path metric, and the other ACS input unit executes the ACSoperation using a value obtained by adding the second branch metric tothe first path metric and a value obtained by adding the first branchmetric to the second path metric.
 3. The processing unit according toclaim 2, wherein said path metric storage apparatus comprises a RAMhaving four banks, stores the path metrics at addresses of therespective banks, and reads two path metrics stored at continuousaddresses.
 4. The processing unit according to claim 2, wherein saidpath metric storage apparatus comprises a dual port RAM having threebanks, stores the path metrics at addresses of the respective banks,reads two path metrics stored at continuous addresses, and writes saidpath metrics to said RAM at the same cycle as the reading.
 5. Theprocessing unit according to claim 2, further comprising input registerswherein two path metrics output from said path metric storage apparatusare input once to said input registers.
 6. The processing unit accordingto claim 2, wherein said branch metric storage apparatus directlyoutputs the branch metrics of double-precision data and swaps a highorder position and a low order position so as to output the branchmetrics.
 7. A processing unit comprising: a path metric storageapparatus that stores path metrics; branch metric storage apparatus thatstores branch metrics; and two ACS input units that input two pathmetrics and two branch metrics to execute ACS operations, and forwriting operation results to said path metric storage apparatus, whereineach of said two ACS input units comprises a comparator apparatus thatcompares two path metrics with two new path metrics generated from twobranch metrics, an adder for generating two new path metrics from twopath metrics and two branch metrics, a selector apparatus that selectseither one of two new path metrics output from said adder based on acomparison result of said comparator apparatus, and a comparison resultstorage apparatus that stores the comparison result of said comparatorapparatus.
 8. The processing unit according to claim 7, wherein one ofsaid comparator apparatus and one of said adders directly input thebranch metrics of double-precision data and swap a high order positionand a low order position so as to input the branch metrics.
 9. Theprocessing unit according to claim 7, wherein one of said comparatorapparatus and one of said adders directly input the path metrics ofdouble-precision data and swap a high order position and a low orderposition so as to input the path metrics.
 10. The processing unitaccording to claim 7, wherein at least one of said two comparators is anarithmetic operation device.
 11. The processing unit according to claim7, wherein at least one of said two comparators is a compressor and anarithmetic operation device.
 12. The processing unit according to claim7, wherein at least one of two adders is a plurality of full adders, andpropagation of a carry signal output from a part of said fall adders toa next stage is controlled.
 13. The processing unit according to claim7, wherein said comparison result storage apparatus comprises shiftregisters.
 14. The processing unit according to claim 7, wherein saidcomparison result storage apparatus inputs a code of a negative value ofthe comparison result.
 15. A mechanical readable recording mediumwherein a program, in which the processing unit described in claim 2 isrealized by software, has been recorded.
 16. A radio communicationmobile station apparatus for executing a decode processing of a receivedsignal in the processing unit described in claim
 2. 17. A CDMA mobilestation apparatus for performing a modulation and demodulation by a CDMAsystem and for executing a decode processing of a received signal in theprocessing unit described in claim
 2. 18. A radio communication basestation apparatus for executing a decode processing of a received signalin the processing unit described in claim
 2. 19. A CDMA base stationapparatus for performing a modulation and a demodulation by a CDMAsystem and for executing a decode processing of a received signal in theprocessing unit described in claim
 2. 20. A radio communication systemwherein the processing unit described in claim 2 is mounted on at leastone of a mobile station apparatus and a base station apparatus.
 21. ACDMA radio communication system for performing a modulation anddemodulation by a CDMA system wherein the processing unit described inclaim 2 is mounted on at least one of a mobile station apparatus and abase station apparatus.
 22. A processing method comprising the steps of:reading two stored path metrics representing the states of 2N and 2N+1,where N=0,1, . . . , 2^(k−2)−1 and where K represents a constraintlength and two stored branch metrics; executing ACS operations inparallel using the read two path metrics and the two read branchmetrics; and writing an operation result to a path metric storageapparatus.
 23. A processing method comprising the steps of: reading twopath metrics stored and two branch metrics stored; executing ACSoperations in parallel using the two read path metrics and the two readbranch metrics; and writing an operation result to a path metric storageapparatus; wherein a value, which is obtained by adding a first branchmetric to a first path metric, and a value, which is obtained by addinga second branch metric to a second path metric, are used in one of theACS operations executed in parallel, and a value, which is obtained byadding the second branch metric to the first path metric, and a value,which is obtained by adding the first branch metric to the second pathmetric, are used in the other ACS operation.